module cache_control(
    input reset,
    input clk,
    input [63:0] addr,
    input [1:0] control,
    output hit0,
    output hit1,
    output hit,
    output reg [63:0] write_back_addr,
    output write_way,
    output read_ena,
);

    reg [54:0] tag_arrays_0[0:63];
    reg [54:0] tag_arrays_1[0:63];
    reg age_tag[0:63];

    wire hit;
    wire hit0;
    wire hit1;

    assign hit0 = tag_arrays_0[addr[9:3]][54] == 1'b1 && tag_arrays_0[addr[9:3]][53:0] == addr[63:10];
    assign hit1 = tag_arrays_1[addr[9:3]][54] == 1'b1 && tag_arrays_1[addr[9:3]][53:0] == addr[63:10];
    assign hit = hit0 | hit1;
    assign write_way = age_tag[addr[9:3]];
    assign read_ena = control == 2'b01;

    always @(posedge clk) begin
        if(reset) begin
            genvar i;
	        generate
		        for (i = 0; i < 64; i = i + 1) begin
		        	tag_arrays_0[i] <= 55'd0;
                    tag_arrays_1[i] <= 55'd0;
                    age_tag[i] <= 1'b0;
		        end
	        endgenerate
        end else begin
            if(control == 2'b01) begin
                if(hit) begin
                    if(hit0) begin
                        age_tag[addr[9:3]] <= 1'b1;
                    end else begin
                        age_tag[addr[9:3]] <= 1'b0;
                    end
                end else begin
                    if(write_way) begin
                        tag_arrays_0[addr[9:3]][54] <= 1'b1;
                        write_back_addr <= {tag_arrays_0[53:0], addr[9:3], 3'b000};
                    end else begin
                        tag_arrays_1[addr[9:3]][54] <= 1'b1;
                        write_back_addr <= {tag_arrays_1[53:0], addr[9:3], 3'b000};
                    end
                end
            end else if(control == 2'b10) begin
                if(hit) begin
                    if(hit0) begin
                        age_tag[addr[9:3]] <= 1'b1;
                        tag_arrays_0[addr[9:3]][54] <= 1'b1;
                    end else begin
                        age_tag[addr[9:3]] <= 1'b0;
                        tag_arrays_1[addr[9:3]][54] <= 1'b1;
                    end
                end else begin
                    if(write_way) begin
                        tag_arrays_0[addr[9:3]][54] <= 1'b1;
                        write_back_addr <= {tag_arrays_0[53:0], addr[9:3], 3'b000};
                    end else begin
                        tag_arrays_1[addr[9:3]][54] <= 1'b1;
                        write_back_addr <= {tag_arrays_1[53:0], addr[9:3], 3'b000};
                    end
                end
            end
        end
    end

endmodule